(1) Field of the Invention
The present invention relates to a static-type random-access memory (RAM) device and more particularly to a static-type RAM device such as a metal-insulator semiconductor (MIS) memory device in which the amplitude of the data signal in a memory cell just after the writing of data thereinto is completed is increased and the stability of the data stored in the memory cell is increased.
(2) Description of the Prior Art
In a semiconductor memory device, it is possible for the data stored in each memory cell to sometimes be destroyed due to the irradiation of alpha rays thereinto or due to the application of noises thereto. The destruction of data occurs more frequently when the amplitude of the data stored in each memory cell, i.e., the voltage difference between the high level portion and the low level portion of each memory cell, is small. Therefore, it is necessary to increase the amplitude of the data stored in each memory cell as much as possible although the potential of the power source is limited to a predetermined value.
FIG. 1 is a circuit diagram of a conventional static-type RAM device (hereinafter referred to as a static RAM device). In FIG. 1, MC is a memory cell composed of four MIS transistors Q.sub.1 through Q.sub.4 and two resistors R.sub.1 and R.sub.2. BL and BL are bit lines, WL is a word line, and DB and DB are data buses. Q.sub.5 and Q.sub.6 are transistors constituting column-selecting transfer gates connected between the bit lines BL and BL and the data buses DB and DB, respectively. Q.sub.11 and Q.sub.12 are load transistors connected between the bit lines BL and BL and a power source V.sub.cc, and Q.sub.7 through Q.sub.10 are transistors constituting a write-in circuit WTC. RD is a row decoder, and RB is a row driver composed of transistors Q.sub.13 and Q.sub.14. One end of each of the data buses DB and DB is connected to a sense amplifier SA (not shown in the drawing). In FIG. 1, only one memory cell MC, only one pair of bit lines BL and BL, and only one word line WL are illustrated. In practice, however, a plurality of memory cells, bit line pairs, and word lines are arranged.
In the static RAM device of FIG. 1, when data is written into the memory cell MC, a row-selecting signal X having a high potential level obtained by inverting and amplifying the output of the row decoder RD, is applied to the word line WL, and a column-selecting signal Y having a high potential level is applied to the gate electrodes of the column-selecting transistors Q.sub.5 and Q.sub.6 by a column decoder (not shown). Thus, the transistors Q.sub.3 and Q.sub.4 of the memory cell MC and the column-selecting transistors Q.sub.5 and Q.sub.6 are all turned on. Therefore, the data buses DB and DB and the bit lines BL and BL are connected, respectively, and the bit lines BL and BL and the nodes A and B of the memory cell MC are connected, respectively. In this condition, a write-enable signal WE is rendered low, and write-in signals IN and IN are rendered, for example, low and high, respectively, and are applied to the write-in circuit WTC. In this condition, the transistors Q.sub.7 and Q.sub.10 of the write-in circuit WTC are turned on and the transistors Q.sub.8 and Q.sub.10 thereof are turned on, thereby rendering the potentials of the data buses DB and DB high and low, respectively, and rendering the potentials of the bit lines BL and BL high and low, respectively. Therefore, the transistor Q.sub.1 of the memory cell MC is turned on and the transistor Q.sub.2 of the memory cell MC is turned off, with the result that the potentials of the nodes A and B of the memory cell MC become low and high, respectively. FIG. 2 illustrates the waveforms at the signals of each node when the data "1" or "0", which is opposite to the data "0" or "1" which is initially stored in the memory cell MC, is written into the memory cell.
The potential of the high level portion of the memory cell into which the information has just been written, i.e., the potential of the above-mentioned node B, becomes lower than the power supply voltage V.sub.cc. As is illustrated in FIG. 2, when the write-in signal IN changes from a low level potential to a high level potential which is approximately equal to the power supply voltage V.sub.cc, the potential of the data bus DB rises from a low level potential to the potential V.sub.cc -V.sub.th (Q.sub.7), i.e., the potential which is attained by subtracting the threshold voltage V.sub.th (Q.sub.7) of the transistor Q.sub.7 from the power supply voltage V.sub.cc. The potential of the bit line BL becomes V.sub.cc -V.sub.th (Q.sub.6) when the threshold voltage V.sub.th (Q.sub.6) of the transistor Q.sub.6 is larger than the threshold voltage V.sub.th (Q.sub.7) and becomes V.sub.cc -V.sub.th (Q.sub.7) when V.sub.th (Q.sub.6) is smaller than V.sub.th (Q.sub.7). Therefore, the potential V.sub.B of the above-mentioned node B becomes EQU V.sub.B =V.sub.cc -V.sub.th (Q.sub.4,Q.sub.6,Q.sub.7)
where V.sub.th (Q.sub.4, Q.sub.6, Q.sub.7) is the largest threshold voltage among the threshold voltages V.sub.th (Q.sub.4), V.sub.th (Q.sub.6), and V.sub.th (Q.sub.7) of the transistors Q.sub.4, Q.sub.6, and Q.sub.7, and it is assumed that the potentials of the high level signals of the word line WL, the write-in signals IN and IN, and the column-selecting signal Y all rise to approximately the power supply voltage V.sub.cc.
The potential V.sub.B of the node B, i.e., the node of the memory cell which is rendered high by the above-mentioned write-in operation, rises toward the power supply voltage V.sub.cc by the time constant R.multidot.C after the write-in operation is finished due to the supply of electric charges through the load resistor R.sub.2 of the memory cell. In this case, R=R.sub.1 =R.sub.2, and C is the stray capacitance of the node B. In a recent static RAM device, since the value of the resistance R is determined to be on the order of more than a gigohm in order to decrease power consumption, the time constant R.multidot.C is relatively large. Therefore, in the above-mentioned conventional static RAM device, the time interval from the completion of the writing of data into the memory cell to the time when the potential of the high level portion of the memory cell is almost equal to the power supply voltage V.sub.cc becomes long. Thus, in the conventional static RAM device, the stored data is often destroyed by external noises, alpha rays, and so on which are irradiated into the memory cell during the above-mentioned time interval.